DE 10 2011 013 228 A1 discloses a manufacturing method for semiconductor devices. Two stop layers are arranged on a passivation layer above a semiconductor substrate. A handling wafer is applied and thinned until the upper stop layer is reached. The upper stop layer is then removed selectively with respect to the lower stop layer, which can be TiN or tungsten. The passivation layer and the lower stop layer cover an area above a through-substrate via.
WO 2012/031845 A1 discloses a manufacturing method for semiconductor devices with a through-substrate via. A metal plane embedded in a dielectric layer is arranged on a semiconductor substrate. A base substrate comprising a contact area on an insulated connection metal plane is connected to the semiconductor substrate. A contact hole is formed through the dielectric layer and the semiconductor substrate, and the contact area is thereby exposed. A metallization is applied to form a connection contact on the contact area and a through-contact in the contact hole.
If a through-silicon via is completely filled, it may be damaged by thermomechanical stress between the filler and the silicon owing to different coefficients of thermal expansion. For reference see the publication of M. Bouchoucha et. al., “Reliability Study of 3D-WLP Through Silicon Via with Innovative Polymer Filling Integration”, 2011 IEEE 61st Electronic Components and Technology Conference, pp. 567-572.